This invention relates to a semiconductor device including two semiconductor switches connected in series which are each provided with an antiparallel connected recovery diode, as well as a first terminal between the two semiconductor switches and two terminals for supplying an intermediate circuit voltage.
A circuit configuration comprised of these components has been described for instance, in the magazine "Elektronik" 1980, issue 24, pp. 91-94, specifically in connection with illustration (Bild) 3. This circuit configuration in particular finds application in inverters. The switches are triggered by means of impulses, with a frequency which is high in comparison with that of the voltage which is to be generated at the load. This produces problems which are described in connection with FIG. 1.
FIG. 1 illustrates a bridge arm of an inverter whose semiconductor switches respectively take the form of a transistor T1 or T2. The collector of the transistor T1 is designated as C1 and is connected to an input terminal 1 via an inductance L.sub.s which represents the entire leakage inductance of the circuit. The emitter is designated as E1. The emitter E2 of the transistor T2 is connected to an input terminal 2. The collector C2 of transistor T2, and also E1, are connected to the terminal 3. Connected to the terminal 3 is an inductive load L whose terminal is connected with the terminal 2 via another transistor T3. Between the terminals 1 and 2 there is an intermediate circuit voltage U.sub.ZW. The diodes D1 or D2 are connected in antiparallel fashion to the transistors T1, T2.
In explaining the function, it is assumed that T1 is conductive. A current I.sub.L flows in the direction of the arrow through the load L. When T1 is cut off and becomes nonconductive, the voltage across L drives a freewheeling current I.sub.F through T3 and T2. This current is represented by a dot-dash line. If, during the next cycle T1 is again turned on, the current I.sub.1 passing through T1 increases. As the current I.sub.L passing through L, which is related to the clock rate of the circuit, is essentially constant, the diode current I.sub.D =I.sub.L -I.sub.1 decreases. Since the diode D2 is then flooded with charge carriers, part of I.sub.1 flows in the form of a return current I.sub.R (broken arrow) through D2 to the terminal 2.
The foregoing condition is illustrated in FIG. 2 by means of plots of current and voltage waveforms versus time. Here, the voltage UT.sub.1 is applied to T1; the current I.sub.1 and the voltage UD.sub.2 to D2. The diode current I.sub.D results from I.sub.L -I.sub.1. The diode current I.sub.D, which thus flows as the return current, assumes values which are considerably higher than the load current. As the return current increases, the diode picks up reverse voltage (U.sub.D2), and the return current decreases. As the current I.sub.1 decreases, a voltage peak-caused by leakage inductance L.sub.s -occurs at D2, and is considerably higher than the intermediate circuit voltage U.sub.ZW.
Due to the high diode voltage and the high return current, the dynamic blocking capability of the diode may be exceeded and the diode destroyed. The voltage peak can be reduced by means of an RCD wiring parallel to the diode. However, this wiring produces additional losses and limits the frequency range.